View MC74HC574A05_746159.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC74HC574A Octal 3-State Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The MC74HC574A is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Data meeting the set-up time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be stored even when the outputs are not enabled. The HC574A is identical in function to the HC374A but has the flip-flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.
Features http://onsemi.com MARKING DIAGRAMS
20 PDIP-20 N SUFFIX CASE 738 1 1 20 20 1 SOIC-20 DW SUFFIX CASE 751D 1 74HC574A AWLYYWWG MC74HC574AN AWLYYWWG
20
* * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 266 FETs or 66.5 Equivalent Gates Pb-Free Packages are Available
20 20 1 TSSOP-20 DT SUFFIX CASE 948E 1 HC 574A ALYWG G
20 1
20 SOEIAJ-20 F SUFFIX CASE 967 1
74HC574A AWLYWWG
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
July, 2005 - Rev. 10
Publication Order Number: MC74HC574A/D
MC74HC574A
OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK OE L L L H
FUNCTION TABLE
Inputs Clock D H L X X Output Q H L No Change Z
L,H, X
X = Don't Care Z = High Impedance
Figure 1. Pin Assignment
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK OUTPUT ENABLE
2 3 4 5 6 7 8 9 11 1
19 18 17 16 15 14 13 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
PIN 20 = VCC PIN 10 = GND
Figure 2. Logic Diagram
Design Criteria Internal Gate Count*
Value 66.5 1.5 5.0
Units ea. ns
I IIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIII IIIIIIIIIIIIII II IIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIII II I IIIIIIIIIIIIIII II IIIIII II IIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIII
Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product mW pJ 0.0075 *Equivalent to a two-input NAND gate.
http://onsemi.com
2
MC74HC574A
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance PDIP SOIC TSSOP PDIP SOIC TSSOP (Note 1) Parameter Value *0.5 to )7.0 *0.5 to VCC )0.5 *0.5 to VCC )0.5 $20 $35 $35 $75 $75 *65 to )150 260 )150 67 96 128 750 500 450 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) UL 94 V-0 @ 0.125 in >4000 >300 >1000 V Unit V V V mA mA mA mA mA _C _C _C _C/W
PD
Power Dissipation in Still Air at 85_C
mW
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
$300 mA Above VCC and Below GND at 85_C (Note 5) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78. 6. For high frequency or heavy load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). ILatchup Latchup Performance
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI, VO TA tr, tf DC Supply Voltage DC Input Voltage, Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Parameter (Referenced to GND) (Referenced to GND) Min 2.0 0 *55 0 0 0 Max 6.0 VCC )125 1000 500 400 Unit V V _C ns
7. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level.
http://onsemi.com
3
MC74HC574A
ORDERING INFORMATION
Device MC74HC574AN MC74HC574ANG MC74HC574ADW MC74HC574ADWG MC74HC574ADWR2 MC74HC574ADWR2G MC74HC574ADTR2 MC74HC574ADTR2G MC74HC574AF MC74HC574AFG MC74HC574AFEL MC74HC574AFELG Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 18 Units / Box 18 Units / Box 38 Units / Rail 38 Units / Rail 1000 Tape & Reel 1000 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 40 Units / Rail 40 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions Vout = VCC - 0.1 V |Iout| v 20 mA VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 Guaranteed Limit *55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 v85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 v125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 Unit V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II II I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I IIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I II II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II
VIL Maximum Low-Level Input Voltage Vout = 0.1 V |Iout| v 20 mA V VOH Minimum High-Level Output Voltage Minimum High-Level Output Voltage Vin = VIH |Iout| v 20 mA Vin = VIH V VOH |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 2.48 3.98 5.48 0.1 0.1 0.1 2.34 3.84 5.34 0.1 0.1 0.1 V VOL Maximum Low-Level Output Voltage Vin = VIL |Iout| v 20 mA Vin = VIL V |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 0.26 0.26 0.26 0.33 0.33 0.33 Iin Maximum Input Leakage Current Maximum Three-State Leakage Current Vin = VCC or GND $0.1 $0.5 $1.0 $5.0 $1.0 $10 mA mA IOZ Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 40 160 mA 8. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
http://onsemi.com
4
MC74HC574A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 3 and 6) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit *55 to 25_C 6.0 15 30 35 v85_C 4.8 10 24 28 v125_C 4.0 8.0 20 24 Unit MHz
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II II I I I III I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I I I II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I II II I II I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures 3 and 6) 160 105 32 27 150 100 30 26 140 90 28 24 60 27 12 10 10 15 200 145 40 34 190 125 38 33 175 120 35 30 75 32 15 13 10 15 240 190 48 41 225 150 45 38 210 140 42 36 90 36 18 15 10 15 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 4 and 7) ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 4 and 7) 2.0 3.0 4.5 60 2.0 3.0 4.5 6.0 ns tTLH, tTHL Maximum Output Transition Time, any Output (Figures 3 and 6) ns Cin Maximum Input Capacitance pF pF Cout Maximum Three-State Output Capacitance, Output in High-Impedance State 9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 24 CPD Power Dissipation Capacitance (Per Enabled Output)* pF *Used to determine the no-load dynamic power consumption: P D = C PD V CC2 f + I CC V CC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed Limit VCC Symbol tsu Parameter Figure 5 Volts 2.0 3.0 4.6 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C Min 50 40 10 9.0 5.0 5.0 5.0 5.0 75 60 15 13 Max v 85_C Min 65 50 13 11 Max v 125_C Min 75 60 15 13 Max Unit ns
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I IIII I I I I I IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII III I
Minimum Setup Time, Data to Clock th Minimum Hold Time, Clock to Data 5 5.0 5.0 5.0 5.0 95 80 19 16 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock 3 110 90 22 19 ns tr, tf Maximum Input Rise and Fall Times 3 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns
http://onsemi.com
5
MC74HC574A
SWITCHING WAVEFORMS
tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL tf VCC GND 1.3 V GND tPZL Q 1.3 V tPZH Q tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE 3.0 V
Figure 3.
Figure 4.
TEST POINT
VALID VCC DATA 50% GND tsu CLOCK th VCC 50% GND DEVICE UNDER TEST
OUTPUT
CL*
*Includes all probe and jig capacitance.
Figure 5.
Figure 6.
C Q D C Q D C Q D C Q D C Q D C Q D C Q D C Q D 11 1 19
D0
2
Q0
D1
3
18
Q1
D2
4
17
Q2
TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
D3
5
16
Q3
D4
6
15
Q4
CL*
D5 *Includes all probe and jig capacitance. D6
7
14
Q5
8
13
Q6
Figure 7. Test Circuit
D7 9 12 Q7
CLOCK OUTPUT ENABLE
Figure 8. Expanded Logic Diagram http://onsemi.com
6
MC74HC574A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11
B
10
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
C
L
DIM A B C D E F G J K L M N
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
http://onsemi.com
7
L
MC74HC574A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE B
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
http://onsemi.com
8
IIII IIII IIII
SECTION N-N M DETAIL E
2X
L/2
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC574A
PACKAGE DIMENSIONS
SOEIAJ-20 F SUFFIX CASE 967-01 ISSUE O
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 0_ 10 _ 0.028 0.035 --- 0.032
b 0.13 (0.005)
M
A1 0.10 (0.004)
http://onsemi.com
9
MC74HC574A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
10
MC74HC574A/D

▲Up To Search▲

Price & Availability of MC74HC574A05

	To Download MC74HC574A05 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .